1. Field of the Invention
The present invention relates to a non-volatile memory system, and in particular, to a non-volatile memory system having a pseudo pass function.
2. Description of the Related Art
If a non-volatile semiconductor memory device, for example, NAND flash memory, is used, bit error detection and correction by error checking and correcting (ECC) are effective for ensuring sufficient reliability. For example, a standard system using a multi-value NAND flash memory has a built-in ECC, which enables four-symbol bit error detection and correction per page.
High integration and large capacity have advanced in the NAND flash memory. In a NAND flash memory having such high integration and large capacity, the following phenomenon has recently been confirmed. According to the phenomenon, the threshold value of a certain memory cell suddenly becomes high; as a result, data is not correctly written or erased. This phenomenon is called “sudden bit error” in the following description.
The address at which the foregoing sudden bit error occurs is completely random, and the cause is not related to the operational history. However, sudden bit error is possibly related to the aging degradation of a memory cell. Even if sudden bit error occurs, data is erased, and thereafter, the data is again written, and thereby, recovery is made. Judging from the peculiarity described above, sudden bit error is not a phenomenon which happens resulting from fatal failure of the memory cell, but is considered a soft error. There exists no way to effectively prevent sudden bit error at present.
Sudden bit error occurs in non-volatile semi-conductor memory devices using the same non-volatile memory cell as NAND flash memory regardless of the NAND flash memory. There is a possibility of a serious problem arising in a multi-value memory having a data corresponding threshold distribution range severer than a normal two-value memory.
In view of the foregoing circumstances, the following concept has been proposed. For example, in the multi-value NAND flash memory, it is advantageous in cost to allow sudden bit error to some degree to ensure reliability. A function developed based on the foregoing concept is a so-called the “pseudo pass function”. The pseudo pass function is a method of returning a “pass” as the status even if a bit error occurs in one or two bits when a chip internal write or erase sequence is completed. For example, the foregoing method has been disclosed in U.S. Pat. No. 6,185,134 and Japan Patent Registration No. 3178912. More specifically, even if the bit error occurs when a chip internal write or erase sequence is completed, ECC is carried out in a system or flash controller in the read operation. For this reason, no hindrance is given so long as the bit error is within a range of the number of correctable bits.
However, if the foregoing pseudo pass function is employed, all bits must be given as correct data when a chip internal write or erase sequence is completed. For this reason, the probability of causing a bad block is readily enhanced as compared with the case where no pseudo pass function is employed. As a result, there is a problem that available memory capacity is easily reduced.
Reference documents:
U.S. Pat. No. 6,185,134
JPN. Patent Registration No. 3178912